library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity  maincontrol is
	port (
		z: IN STD_LOGIC;
		opcode, func: IN STD_LOGIC_VECTOR (5 downto 0);
		jump, branch, memtoreg, writemem, writereg, regdes, alusrcb, se: out std_logic;
		aluctr: out std_logic_vector (4 downto 0)
	);		
end maincontrol;


architecture maincontrol_arch of maincontrol is
	signal special, add, op_or, lw, sw, addi, ori, beq, bne, j: std_logic;
begin
	--TODO: WRITE YOUR CODE HERE
	special <= '1' when opcode="000000" else '0';
	add <= '1' when  special&func="1100000" else '0';
	op_or <= '1' when special&func="1100101" else '0';
	lw <= '1' when opcode="100011" else '0';
	sw <= '1' when opcode="101011" else '0';
	addi <= '1' when opcode="001000" else '0';
	ori <= '1' when opcode="001101" else '0';
	beq <= '1' when opcode="000100" else '0';
	bne <= '1' when opcode="000101" else '0';
	j <= '1' when opcode="000010" else '0';
	jump <= j;
	branch <= (z and beq) or (not z and bne);
	writereg <= add or op_or or addi or ori or lw;
	regdes <= special;
	writemem <= sw;
	memtoreg <= lw;
	aluctr(4) <= '0';
	aluctr(3) <= op_or or ori or beq or bne;
	aluctr(2) <= '0';
	aluctr(1) <= '0';
	aluctr(0) <= add or lw or sw or addi or beq or bne;
	alusrcb <= addi or ori or lw or sw;
	se <= addi or lw or sw or beq or bne;
end maincontrol_arch;
